Understanding Read Noise in sCMOS

sCMOS technology boasts an ultra-low read noise floor that significantly exceeds that of even the best CCDs, and at several orders of magnitude faster pixel readout speeds. For those more accustomed to dealing with CCDs, it is useful to gain an understanding of the nature of read noise distribution in CMOS imaging sensors.

CCD architecture is such that the charge from each pixel is transferred through a common readout structure, at least in single output port CCDs, where charge is converted to voltage and amplified prior to digitization in the Analog to Digital Converter (ADC) of the camera. This results in each pixel being subject to the same readout noise. However, CMOS technology differs in that each individual pixel possesses its own readout structure for converting charge to voltage. In the sCMOS sensor, each column possesses dual amplifiers and ADCs at both top and bottom (facilitating the split sensor readout). During readout, voltage information from each pixel is fed directly to the appropriate amplifier/ADC, a row of pixels at a time .